Clock signals are typically used to establish the timing of a digital signal or the timing at which an operation is performed on a digital signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with an internal clock signal such as a data strobe signal. A write strobe signal, during a write data operation, typically has a phase that is aligned with a system clock signal. The write strobe signal may be generated by the memory controller derived from the system clock signal, and is applied to the memory device into which the data are being written. Write data signals are conventionally applied in synchronism with the write strobe signal. For example, the write data signals are captured responsive to the write strobe signal transitions between two logic states during a “data eye” occurring at the center of the period in which the write data signals are valid. The write strobe signal can therefore be used by a memory device to capture the write data when the data are valid.
As the speed of memory devices continue to increase, the timing of write strobe signals relative to the tracking and timing of the data signals has become even more critical. Conventional write latency tracking systems may utilize frequency dividers to generate multi-phase write strobe signals that may be used to track the data signals and alleviate some of the timing constraints. The write strobe signal may be issued intermittently by the memory controller in the form of burst data during a write operation. Data bits (also referred to as digits) initially collected from a high-speed serial link during a write operation may be deserialized to reduce the frequency at which the data bits are provided for better handling of the data by the DRAM device. Thus, the use of multi-phase strobe signals allow for a larger bandwidth and increased timing margin as more data may be captured at a faster rate.
The problem with conventional write latency tracking systems that employ frequency dividers is that synchronization between the system clock and the write strobe signal is not easily attained due to the write strobe signal being discontinuous while the system clock is continuous. Utilizing synchronous dividers may simplify frequency division and write strobe signal distribution, but it also results in an indeterministic phase sequence between the continuous system clock and the discontinuous divided write strobe signals. The problem is exacerbated by write strobe preamble transitions necessary for non-consecutive write commands, which may cause further tracking misalignment. Consequently, a difficulty with using the multi-phase write strobe has been with tracking the correct data and aligning the data between the frequency divided strobe signals and the system clock. Other factors, such as statistical variations in transistor characteristics, voltage gradients across the integrated circuit die, and data dependent switching noises may contribute to timing problems and may cause significant delay mismatch in nominally matched circuit paths.
There is, therefore, a need in the art for a write latency tracking system that tracks the timing of when data arrives and captures the data relative to a discontinuous write strobe signal.